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DNguy11's avatar
DNguy11
Icon for New Contributor rankNew Contributor
6 years ago

How to write a Verilog to implement -MULT(27x27) so that QPRO map the full functionality to 1 DSP?

Using QPRO it is possible to build an IP to implement -(X*Y) where X and Y are of 27 bit-width. However I find NO verilog writing style such that QPRO is able to map the full functionnality within 1 ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

What device that you were using? You will first need to understand the architecture of the DSP. You can look into it in the resource property editor.

With that said, you can look into how to write the code in right click the verilog.v files -> insert template -> Verilog HDL -> Full Designs -> Arithmetic -> DSP features

Thanks

DNguy11's avatar
DNguy11
Icon for New Contributor rankNew Contributor
6 years ago

Issue is with any stratix10 device. I already used the resource-property-editor to implement -(aXb) using the negate of the mult + the load_const of the DSP. So the solution is feasible. I already looked at the possible templates but nothing is proposed to implement -(A*B) within a single DSP