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LChen23
New Contributor
New ContributorHow to workaround the ERROR ID:18694
Hi, When I switch Quartus from 18.1std to 19.4 Pro,Quartus report an error, The ID is ID:18694 ID:18694 The reference clock on PLL "<name>", which feeds an Altera LVDS SERDES IP instance, is not d...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
Kindly fine the inline reply
CAUSE: PLLs driving LVDS SERDES interfaces should use dedicated reference clock pins from the same bank. Using a different source such as a global clock or PLL cascading can add extra jitter and has not been fully verified and characterized by Intel. It is therefore not guaranteed to meet its max data rate specification.
ACTION: Use a dedicated reference clock pin per PLL that drives an Altera LVDS SERDES IP instance.
