How to workaround the ERROR ID:18694

Hi ,

Kindly fine the inline reply

CAUSE: PLLs driving LVDS SERDES interfaces should use dedicated reference clock pins from the same bank. Using a different source such as a global clock or PLL cascading can add extra jitter and has not been fully verified and characterized by Intel. It is therefore not guaranteed to meet its max data rate specification.

ACTION: Use a dedicated reference clock pin per PLL that drives an Altera LVDS SERDES IP instance.