Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi kaushalyas,
I use to parameterize my bdf designs with the PARAM primitive just as you can see in the attached files. This bdf example generates no error when compiled and I haven't generate any HDL to check as the implementation has proven to performed properly once downloaded into the FPGA ! Regarding your problem, have you put the PARAM in the pin name of your input/output primitive connected to your bus as well ?