Honored Contributor
Honored ContributorHrmmm...Are we getting different results or is my understanding flawed? I just downloaded the zipped file on a different computer, built with Quartus Prime Version 16.1.0 Build 196, and without changing anything (just double clicking "Compile Design") I get a failed timing result under "Fast 1200mV 0C Model." Here are the results of the worst case timing:
Slack: -0.457 From Node: iop_slv_DQ[0] To Node: Test:Lower_DQ_BIDIR|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_prr:auto_generated|input_cell_l[0] Launch Clock: virt_clk Latch Clock: CLK_ddr_ldqs_n Relationship: 0.000 Clock Skew: 1.743 Data Delay: 1.307 But you got nothing? Weird.... Also, I'm a bit confused on your statement that an input delay of 0 would be the best case for setup time? Did you mean an input delay of 0 on the data pins (DQ) as opposed to the clock pin (DQS)? In my mind, delaying the clock would make the data arrive "earlier" relative to the clock, which would help meet setup instead of hurt. This seems to be what the an348 was getting at as well.
