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AZahe1's avatar
AZahe1
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6 years ago

How to use the SCLR port of a flip flop in VHDL?

Hi, I am new in VHDL and the Quartus software. I was designing a simple flip flop circuit with synchronous clear by using sequential VHDL, but in the RTL schematic, it looks like it added a multipl...
sstrell's avatar
sstrell
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6 years ago

sclr is active high, so your if check should be if sclr = '1'. Also, there's no need for the extra qs signal. Just make the assignments to q in the process.

#iwork4intel

  • AZahe1's avatar
    AZahe1
    Icon for New Contributor rankNew Contributor
    6 years ago

    thank you for replying.

    I changed the reset to be active high, but it still uses extra logic. the only difference is that the inputs of the multiplexers have flipped.

    yes right, I too think there is no need for the qs signal here.