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Altera_Forum's avatar
Altera_Forum
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15 years ago

how to use test bench file(.vhd) to simulate

Hi,

I'm a beginner of VHDL and quartusII. Now I want to continue with someone else's work and since that i don't have the right FPGA board to test, the only thing I have is a test bench file in 'vhd'. But I don't know how to do with it. Is there a way that i can convert this file into waveform file so that I can simulate it in quartusII? I've seen some comments talking about using ModelSim(setting->simulation->test bench). But the ugly thing is that I have quartus 7.2 in windows and modelsim in linux, seperately... so I cannot use 'run EDA RTL simulation' which calls modelsim from quartus, as stated in someone's comments.

Does anyone have some idea? sorry if the question is so simple, I'm really a new comer.

Thanks a lot.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi,

    I think the "native link" feature, that allowed ModelSim-Altera to be started directly from Quartus, was a bit broken.

    My suggestion: just use ModelSim by itself.

    Create a new project, load all you VHDL (testbench and rtl) and simulate it.

    IIRC, with ModelSim-Altera, Altera's libraries will already be loaded when you start ModelSim.

    ModelSim comes with some documentation of it's own.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Hi,

    I think the "native link" feature, that allowed ModelSim-Altera to be started directly from Quartus, was a bit broken.

    My suggestion: just use ModelSim by itself.

    Create a new project, load all you VHDL (testbench and rtl) and simulate it.

    IIRC, with ModelSim-Altera, Altera's libraries will already be loaded when you start ModelSim.

    ModelSim comes with some documentation of it's own.

    --- Quote End ---

    thanks, I use ModelSim alone now and I've found a document very helpful.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    We are VLSI design center and we made several designs before, using FPGAs, by writing the required codes and testbench for functional and timing simulation of the design, then download the design on the hardware . Currently we have a design that uses IPs only . We implemented it using SOPC builder and we have also a development board for hardware testing .

    My question is : do we need to write the testbench for this design in order to perform functional simulation first then download it on the development board ? or can we skip the functional simulation since the design consists of IPs only and these IPs are tested by Altera?