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Ryan-SEU's avatar
Ryan-SEU
Icon for New Contributor rankNew Contributor
3 years ago

How to use modelsim to do RTL simulation of DDR3 with UniPHY

Hi everyone, Environment : WIN10 64bits, Quartus II 18.1, modelsim-altera 10.5b, cyclone V E 5CEFA9F31I7N, Micron MT41J128M16JT-125*2. I am a FPGA beginner. In my design, I used two Micron DDR3...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Ryan,


When generating the example design, you can choose either synthesis or simulation or both of them.

Then the Quartus will generate the design accordingly.

For the simulation file, the Quartus will generate a tcl script for each simulator.

The script should has the library for the initialization and calibration flow of the DDR3.

You can run the generated script to test the design.


Regards,

Adzim


  • Ryan-SEU's avatar
    Ryan-SEU
    Icon for New Contributor rankNew Contributor
    3 years ago

    Supplement: In modelsim, you can see that I correctly store the data according to the timing requirements, the read data is always 0. but the data can be correctly retrieved in the Signaltap test.Do you know the possible reason?