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Well, Altera documents are not very easy to read. And there are only few examples. I try my best to get information out of it, but at the moment I haven't found more on how I should handle my arrays to infer them as Memory Blocks. Any Hints?
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Read page 13-13 - "Inferring memory functions from HDL code". I find it rather helpful. But it also helps a lot if you understand the underlying architecture.
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Too bad I can't give you the whole code. Kind of secret stuff. But I can tell you something about it:
I have three processes which are using the arrays.
One process loads the Arrays with data and the other two are reading from them.
All three Processes have different clocks.
The two reading processes are accessing one of the two arrays at the same time while the other array is loaded with data.
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Theres the problem. The memories on the board are dual ported - hence only 2 clocks allowed. And 3 processes does not follow the guidlines (2 processes, 1 for each port if they are separate clocks).
If you could post the code, then we could help further. Why not just make a new file with just the ram in it thats causing the problem and post that. I promise you, ram inference is not that secret and what you are doing has probably been done many times before.
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