Altera_Forum
Honored Contributor
Honored Contributorhow to use clk in fsm
hey..I want to build a final state machine embodies eight numbers and then she proceeded to tell the eighth.For example if the eight number is four I want the machine extract four pulses of 1 clock cycle difference between between pulses and then wait another 10 clock cycles and then switches to the next state( and in the next do the same thing).The problem that he dosent let me use the clock in the states ..Does anyone have an idea what to do?The code
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity pulsim is port( resetN, clk : in std_logic; da : in std_logic_vector(3 downto 0) ; db : in std_logic_vector(3 downto 0) ; dc : in std_logic_vector(3 downto 0) ; dd : in std_logic_vector(3 downto 0) ; de : in std_logic_vector(3 downto 0) ; df : in std_logic_vector(3 downto 0) ; dg : in std_logic_vector(3 downto 0) ; dh : in std_logic_vector(3 downto 0) ; sinus : out std_logic); end pulsim ; architecture behavioral of pulsim is type state_type is (s0,s1,s2,s3,s4,s5,s6,s7); signal current_s,next_s: state_type; signal countera : std_logic_vector(4 downto 0) :=dh &'0' ; signal counterb : std_logic_vector(4 downto 0) :="01010" ; signal cinout : std_logic ; begin process ( resetN , clk) begin if resetN = '0' then current_s <= s0; elsif (rising_edge(clk)) then current_s <= next_s; end if; end process; process (current_s,dh,clk) begin sinus <= cinout ; case current_s is when s0 => --when current state is "s0" if(dh ="1111") then cinout <= '0'; next_s <= s0; else if rising_edge(clk) then if countera /= "00000" then countera <= countera-"00001"; cinout<= not(cinout); counterb<="01010"; elsif (countera = "00000") and (counterb/="00000") then counterb <= counterb-"00001"; cinout <= '0' ; else counterb<="01010"; countera<=dg &'0'; next_s <= s1; end if; end if; end if; when s1 => if rising_edge(clk) then if countera /= "00000" then countera <= countera-"00001"; cinout <= not (cinout) ; counterb<="01010"; elsif (countera = "00000") and (counterb/="00000") then counterb <= counterb-"00001"; cinout <= '0' ; else counterb<="01010"; countera<=df &'0'; next_s <= s2; end if; end if; when s2 => if rising_edge(clk) then if countera /= "00000" then countera <= countera-"00001"; cinout <= not (cinout) ; counterb<="01010"; elsif (countera = "00000") and (counterb/="00000") then counterb <= counterb-"00001"; cinout <= '0' ; else counterb<="01010"; countera<=de &'0'; next_s <= s3; end if; end if; when s3 => if rising_edge(clk) then if countera /= "00000" then countera <= countera-"00001"; cinout <= not (cinout) ; counterb<="01010"; elsif (countera = "00000") and (counterb/="00000") then counterb <= counterb-"00001"; cinout <= '0' ; else counterb<="01010"; countera<=dd &'0'; next_s <= s4; end if; end if; when s4 => if rising_edge(clk) then if countera /= "00000" then countera <= countera-"00001"; cinout <= not (cinout) ; counterb<="01010"; elsif (countera = "00000") and (counterb/="00000") then counterb <= counterb-"00001"; cinout <= '0' ; else counterb<="01010"; countera<=dc &'0'; next_s <= s5; end if; end if; when s5 => if rising_edge(clk) then if countera /= "00000" then countera <= countera-"00001"; cinout <= not (cinout) ; counterb<="01010"; elsif (countera = "00000") and (counterb/="00000") then counterb <= counterb-"00001"; cinout <= '0' ; else counterb<="01010"; countera<=db &'0'; next_s <= s6; end if; end if; when s6 => if rising_edge(clk) then if countera /= "00000" then countera <= countera-"00001"; cinout <= not (cinout) ; counterb<="01010"; elsif (countera = "00000") and (counterb/="00000") then counterb <= counterb-"00001"; cinout <= '0' ; else counterb<="01010"; countera<=da &'0'; next_s <= s7; end if; end if; when s7 => if rising_edge(clk) then if countera /= "00000" then countera <= countera-"00001"; cinout<= not (cinout) ; counterb<="01010"; elsif (countera = "00000") and (counterb/="00000") then counterb <= counterb-"00001"; cinout <= '0' ; else counterb<="01010"; countera<=dh &'0'; next_s <= s0; end if; end if; end case; end process; end behavioral; thanks..
