Forum Discussion
I've heard of case analysis but don't fully understand it, so to be honest, I assume it does something impossible without. That being said, if two clocks go through a mux and there are two generated clocks on that mux output, and those two clocks are in different groups in the set_clock_groups assignment, then they won't be analyzed against each other, and when they connect to other clocks, you will get analysis under both conditions. So my assumption is that you would see both cases properly analyzed, and if you really want to remove one clock from analysis(say it's a test clock and won't properly connect to other logic), then it should be isolated with its own set_clock_groups assignment. That's how I would do it, but believe I am missing something in that analysis, so any further explanation as to what point I missed would be helpful.