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Altera_Forum
Honored Contributor
Honored ContributorHow to time constrain output pin connected to input pin on the same FPGA (design) ?
Hello, My design has output pin SYNC_OUT and input pin SYNC_IN, both synchronous, clocked by same clock. Pins connected externally on PCB with known max and min board delay. How do I cons...
Altera_ForumHonored Contributor
Honored ContributorYes, strange indeed. It's not wire out then back in, those are two chips running the same desing. FPGA-to-FPGA synchronization. Both FPGAs clocked from the same clock. But from timing point of view it is the same as it would be connected to itself.
