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I have a design that I successfully implemented and synthesized on a Cyclone device, and would now like to port it to and asic flow. However, I don't want to re synthesize the original RTL verilog, but would rather try to synthesize the output of Quartus synthesis.
The problem is that the vqm output generates a bunch of lcell primitives that my synthesis program does not recognize. I could not find a synthesizable definition of this primitive. Does it exist?
Is there another flow that would work? Perhaps there is a synthesizable netlist that Quartus can dump before tech mapping that could work?
Thanks a lot in advance...
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Hi,
I don't think that will work at all. When Quartus implemements your design I sure it will use some hardmacros like DSP blocks , PLL's , Memories .... I'm quite sure that whether the vqm nor the vo- Files will be a "pure" netlist, which could be simply re-mapped to an ASIC library. You also should keep in mind, that the ASIC technology ist much faster then the FPGA's. As result you will get an ASIC with a larger size as necessary. The best results you will get by running a new synthesis with an ASIC synthesis tool.
Kind regards
GPK
Honored Contributor
