How to start a new design - best way

As expected the clk management will return to be the most critical part.

As example in the "flat mode" I've an output of a PLL that is a regional clock, but now after the partition division it tell me that cannot fit that in a regional clock.

It seems strange to me, but maybe is because I've keep the PLL in the "Top".

Moreover I've another problem about that resources: PLL!

I mean in my design I've a clk that generate 2 clk output that go to 2 different partition (one is a clock in the block control and another is the clk for the Nios section).

I cannot use another clock because theese 2 part MUST start always and this clock is the only one that is up when I turn on the board.

I know also that is bad to devide the clk input pin into 2 different PLL (that I can easily set in each partition), so what can I do?

And more in general how do you use your PLL in a partitioned design?

As first I started with a Top Down approach that is simple to do some practice (I know for sure that it work in flat mode and all the problem I'll have will be derived by the partitioning approach).

I hope someone could help, I can't believe that I'm the only one that wanna use this approach.