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Altera_Forum
Honored Contributor
13 years agoThank you for your reply. I wrote here a simplified process. I do a slightly different thing.
I have 1 process that puts out 6 terms @100MHz to be subtracted (A,B,C,D,E,F). Since i have a lot of time to do these subtraction ( A-B, C-D, E-F), i would use a single subtractor in multicycle. So when data arrive, i store them in registers then i would start my multicycle process, (start_sub_process) the multicycle process loads data in the sub inputs (in0<= A in1 <=B) and does the subtraction (out <= in0-in1). I repeat this for all the data until i have 3 results that i push out with a "done" singnal. Since the start_sub_process belongs to a 100MHz process, i would expect that this path is analyzed with normal constraints. If i apply constraints from clock enable multicycle example, this path is multicycled