How to solve Error (175001): Could not place Channel PLL when trying to use Cyclone V Native PHY IP?

Hi Abraham,

Thanks for your response. However, it turns out that the issue is related to trying to use the standard 50MHz clock signal to drive a PLL that also feeds the transceiver. It is a known problem but can be easily fixed with an intermediate clock buffer using ALTCLKCTRL IP core as described here:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd03302012_430.html

Now the design compiles and simulates with no issues.

Cheers