Well, it looks like the design cannot fit into the device. You did mention that before you integrated the IP your design had ~805 utilization. That leaves almost no space for the tool to fit the IP and also to do a Place N Route and Timing Analysis.
- Error (11802): Can't fit design in device
This error sums it all up.
You may need to
- Re-design the rest of the code so that it takes lesser resources typically ~60% and then try integrating the IP. But this will still pose problems for Timing as the tool will not have enough resources to proceed with the timing driven place and route, etc.
- Target another larger device in the same FPGA family, one in which your design can fit.
- If you're using another PLL in your design, try and generate the required clock using that PLLs output.
-Abraham
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