Forum Discussion
HHo2
New Contributor
New ContributorHow to solve DDR_core_clock and DDR_phy_clock setup time violate ?
I am platform designer, not so familiar with timing. I use QSYS to have a FPGA design, however, I always have some timing violation between DDR core clock and phy clock. but I can't add pipeline br...
Deshi_Intel
Regular Contributor
Regular ContributorHi HHo2,
Can you check below EMIF spec estimator link to ensure your DDR4 IP configuration is within the spec ?
Once you confirmed you are using valid DDR4 IP setting then you can easily generate DDR4 example design from DDR4 IP using same exact setting. After that, you refer to the example design to get better clue on how to close timing.
Thanks.
Regards,
dlim
