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HHo2
New Contributor
New ContributorHow to solve DDR_core_clock and DDR_phy_clock setup time violate ?
I am platform designer, not so familiar with timing. I use QSYS to have a FPGA design, however, I always have some timing violation between DDR core clock and phy clock. but I can't add pipeline br...
HHo2New Contributor
New ContributorHi @dlim thanks for answer
I have check what you suggest, however, my situation is, the falling path is {from emif|ddr_inst|hmc.amm.data to emif|ddr_inst|phy_register}
this path is generated during compile, so I can't see it in qsys, all I can see is just a bus to EMIF IP.
It's from ddr_inst to IO pad phy_register.
I have try over constraint
if {$::quartus(nameofexecutable) != "quartus_sta"} {set_max_delay -to {board_inst|acl_ddr4?_s10|acl_ddr4?_s10_emif_s10_0|acl_ddr4?_s10_emif_s10_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[?].lane_gen[?].lane_inst|lane_inst~phy_reg1} 3.000ns }
but still won't help.
