Forum Discussion
HHo2
New Contributor
New ContributorHow to solve DDR_core_clock and DDR_phy_clock setup time violate ?
I am platform designer, not so familiar with timing. I use QSYS to have a FPGA design, however, I always have some timing violation between DDR core clock and phy clock. but I can't add pipeline br...
Deshi_Intel
Regular Contributor
Regular ContributorHi HHo2,
DDR core clock is still running on FPGA soft logic. Therefore, you may still be able to add pipeline to it.
You can open QSYS interconnect and check the timing failing path whether able to add pipeline or not. Example as below per attachment.
Thanks.
Regards,
dlim
