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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to simulate schematic design?

The new version Quartus II has removed the vwf file, the simulation need to be done through third party tool like Modelsim. If I do a design through schematic design, how can I simulate it through Mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Conversion to HDL is the only choice if you want to simulate an RTL design. You can compile the design and create a post P&R netlist to simulate, but this is much slower.

The best option may be to forget about schematic altogether and just write the whole thing in HDL in the first place.