Honored Contributor
Honored Contributorif you are interested how much time would it take for signal to go through (B or C) and then enter into register A, for this use "timing simulation" mode in modelsim. in this mode, modelsim thinks about logic gates that are inside altera and simulates results based on the real life delay information.
if you just want to ignore real life transistor delays, and just want to test your logic,and artificially create a virtual delay, use functional simulation mode in modelsim. in this mode only your idea gets simulated. regardless of delays that would occur in real life. i never use this mode since it will not give realistic results, but, its fine for testing the logic of your circuit, and also simulating Artificial delays, in verilog for artificially delaying the action use# sign. for example: # 5 A <= B or C # means wait. 5 means wait for 5 times; and then execute the action. now question comes 5 -what? 5 nanoseconds? or 5 microseconds? or milliseconds? thats why you may need to add special command on top of verilog code, to tell the compiler what is the timescale nano micro or anything else. for this use: `timescale = 1ns/10ps 1ns means that you mean nanosecond timespace. and the one on picosecond side means simulation step. it will make resimulation step forward at each 10ps. use smaller number to get higher simulation detail. but it will increase simulation time. remember, the# 5 or whatever time,# 2# 9, this in real life does not exists. altera does not know what "Time" is. it's a machine. so don't count on using this kind of command in real life. if you want to delay a signal in real life, use LCELL. and delay time of LCELL will vary by temperature of processor itself. each LCELL may give you approximately 0.5ns delay. so if you need 5ns for example, you would actually need to pass signal through 10 LCELLs.but then if you get your device at winter cold place these delays will change by the laws of physics.
