Forum Discussion
ZhiqiangLiang
Occasional Contributor
Occasional Contributorhow to set those parameters of clock crossing bridge?
Hi, My FPGA model is Cyclone 10 LP 10CL120YF484. on Platform Designer, NIOS frequency is 80MHz, and my IP is 160MHz. In NIOS C code, I would like to read/write registers of my IP. In my design, ...
I reviewed some diagrams on the website, and based on what I saw, option 2 is actually the correct setup. The diagrams clearly indicate that option 2 is the proper way to connect.
ZhiqiangLiangOccasional Contributor
Occasional ContributorThank you! your explanation is very clear.
Your comments;
the bridge should be configured with the Nios side as the master clock domain and the IP side as the slave.
In my designed, I tried to connect master and slave of Clock Bridge reversed, but it can be run correctly.
so I got confused. how should I connect master and slave.
solution 1: Clock Bridge master <---> NIOS and Clock Bridge slave <--> my IP.
solution 2: Clock Bridge master <---> my IP and Clock Bridge slave <--> NIOS.
