How to set setup and hold time?

One other thing, once you use the generated clock as the -clock in your set_output_delay, when you run report_timing -setup/-hold -to [get_ports {ssync_outputs[*]}]...

You should see a setup relationship of 90 degrees and hold relationship of -90 degrees. You should also see that the Data Required Path traces the entire path from the clock coming into the FPGA to going out the clock output port(assuming you ran report_timing with -detail set to full_path). Basically this means that your data can be skewed in relation to your clock by +/-90 degrees. Then, as your set_output_delay -max grows larger and the -min value grows smaller, it will cut into this. So, if 90 degrees were 4ns, you would have a setup relationship of 4ns. If your -max value is 2.5ns, that would show up as oExt in your timing report and chew up 2.5ns of that 4ns requirement, leaving 1.5ns for the FPGA to skew its data to clock. (That was quick, so hopefully it makes sense)