How to set setup and hold time?

Thanks for the compliment on the book. I will answer all questions now. : )

For your source-synchronous output, you want to:

1) Put a generated clock on the output port where the -source is the PLL output tap that drives it. It should not be virtual, and you do not need to put a -phase 90 or anything on it since the PLL is doing the 90 degree shift and it's generated clock already describes the 90 degree shift.

2) Do NOT use the dedicated PLL output for the clock going off chip. This is a direct connection from the PLL to the output and will have a considerably different delay than your data going off-chip, where the whole purpose of source-synchronous is that the clock and data delays match each other. There are two workarounds, a) move the clock output to another port or b) instantiate an altddio_out megafunction, where the high port is tied off with VCC and the low port to GND, and the clock drives the select. This just makes a clock going off-chip, just as if you sent it off directly. The difference is that the direct PLL output can't drive the output ddr block, and so rather than using the direct PLL -> output connection, it will use PLL -> global -> DDR -> output connection, which will look a lot like your data output path.