How to set setup and hold time?

Hi, Rysc:

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you tell what data port it is referencing, and TimeQuest knows what clock drives that input register and what input port that clock comes in on, so it binds them that way.

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This explaination does make sense.

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The only time a virtual generated clock would be nice is on source-synchronous outputs

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That's exactly my case. My design could only use one PLL, which has already output 32MHz and 50MHz on internal clock pins.

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I often want to say that the external receiver is doing a 90 degree phase-shift, which could be done with a virtual generated clock.

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I'm considering to use the external clock pin of PLL to output a 50MHz, 90 degree phase-alinged clock. The 50MHz, 0 degree phase-shift internal clock can generate the output data, while 50MHz, 90 degree phase-shift external clock can be output launch clock. So the virtual clock is related to 50MHz, 90 degree phase-shift external clock, and the output_delay can be set to 0ns.

Is this right?

And your book is really a brilliant one.