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I'm afraid your code won't result in anything being written to the SDRAM. Your state machine doesn't do the right things to control the SDRAM.
Have a look, and try to understand,
the sdram state diagram on this page (
http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask/3). I hope it gives you an idea of the work involved.
How much data to you have to store? Could you make use of the FPGA's internal RAM?
Cheers,
Alex
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Alex I reduced my data and I'm using the on-chip RAM now, it compiled and loaded to the board, I'm having a unexpected issue though. Data of the third RAM is wrote with 000000000 all the way in. The first 2 RAMS are filled with the right data.
I tried this program in the modelsim first, and I'm sure the logic is correct. Do you have any ideas?
Also, I wish now to see some kind of report to know the speed of my design to complete the application.
Honored Contributor
