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Honored Contributor
Honored ContributorHow to see the content of the SDRAM in my DE1-SOC while running (JTAG Altera cable) ?
I have made a simple design in Quartus Prime, in verilog code, not using megawizard, but directly accessing the pins of the SDRAM. I am saving 2 x 16 bits binary numbers on 3 of the 4 banks of the SD...
Altera_ForumHonored Contributor
Honored ContributorA 'simple design'...
Have you implemented an SDRAM controller? Does your code issue the necessary refresh cycles etc. to keep your SDRAM happy? Your SDRAM controller, as well as writing to memory, will have to issue the necessary command and refresh cycles to read data from it. Does your 'simple' design do all this? Altera's own SDRAM controller IP is pretty big for a reason. Yes, you can use the In-System memory content editor - but only if you've use the Altera SDRAM controller IP. Cheers, Alex
