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To black-box a hierarchy you still need something to describe it. For example, if I had a module called blaa, I might have a verilog file that says:
module blaa (
input clk, din, a,b,c;
output d,e,f);
endmodule
Note that there are no contents, just the port listing. For VHDL I do something similar and just have it empty between architecture:
ARCHITECTURE empty OF top IS BEGIN
END empty;
That should be enough to get it through analysis and elaboration(and synthesis). A nice trick to get it through the fitter is to run Hierarchy Elaboration, then put all those hierarchies into partitions and set them to Empty. This prevents synthesis across boundaries so anything hooked up to these black-boxes doesn't get synthesized out and you can analyze the rest of the design. (This is a nice trick for faster compiles too, i.e. I might have a large design and the full project, but I only care about a particular hierarchy. Rather than making a new project and trying to convert the timing constraints, etc., I just select a few large hierarchies I don't care about and put them into Empty Partitions. The fitter no longer has to place-and-route them and can quickly fit the parts I care about.)
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Thank you. I hoped that it will require less efforts :)
Honored Contributor
