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Its unlikely that there are glitches on CK. However, your logic might be incorrect, and you are getting a single FPGA clock of CK high followed by low, followed by high for a larger number of FPGA clocks (or vice versa). You might interpret that as a 'glitch', however, its not, its a pulse that your synchronous logic created.
Capture a Signal Tap II logic analyzer trace of CK and look at the signal with an oscilloscope.
Cheers,
Dave
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Yes, Dave, you are right. Actually, there is no glitches appear in simulation after I changed my code as I posted. The question I ask is I just assume there are still glitches.
As you mentioned, now I understand is: if I make my design as I posted, in this case, there should not be any more glitches.
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