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If I replace the combinational logic output to register output like:
always @(posedge clk_fast)
begin
if (counterScan>14 && counterScan<31)
CK<=clk_200ns;
else
CK<=0
end
but there are still glitches, what should I do to remove the glitch?
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Its unlikely that there are glitches on CK. However, your logic might be incorrect, and you are getting a single FPGA clock of CK high followed by low, followed by high for a larger number of FPGA clocks (or vice versa). You might interpret that as a 'glitch', however, its not, its a pulse that your synchronous logic created.
Capture a Signal Tap II logic analyzer trace of CK and look at the signal with an oscilloscope.
Cheers,
Dave
Honored Contributor
