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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

How to remove the glitch like this?

I want to design a control module to scan a image sensor chip. In the design, it needs three clock signals as: load_ck, shift_ck, CK. For scanning each pixel, it cost 32 basic clock cycles, dur...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

If I replace the combinational logic output to register output like:

always @(posedge clk_fast)

begin

if (counterScan>14 && counterScan<31)

CK<=clk_200ns;

else

CK<=0

end

but there are still glitches, what should I do to remove the glitch?

Thanks very much.