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Besides other signals, you are creating CK as a gated clock from clk_200 ns. Without discussing the general timing problems brought up by gated or generated clocks, I see two options to do it in a proper synchronous way:
- have a higher system clock, at least 100 ns period. This won't be a problem unless the 5 MHz clock is your primary input clock
- refer to the gated clock design suggested in the Quartus software handbook. It uses a register clocked at the negative edge to delay the gate signal.
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Thanks very much. I think the 1st option you mentioned is I have posted. Is replacing the combinational logic gated clock with register gated clock a general approach to avoid the glitch?
And do you mean the " Quartus software handbook" is the pdf file I can download from the Altera website?
Thanks again.
Honored Contributor
