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The clocks you are creating:
assign CK=(counterScan>14 && counterScan<31)? clk_200ns:1'b0;
assign load_ck=(counterScan<6)? clk_200ns:1'b0;
assign shift_ck=(counterScan==8)? clk_200ns:1'b0;
are combinatorial. That is the source of your glitches (different combinatorial paths through the device). If this was a post P&R simulation, the glitches would likely be worse.
You need to create the clock signals inside a clocked process in the FPGA, i.e., those clock pulses need to be output from registers in the FPGA.
This means if you need to generate a 10MHz output clock, your FPGA needs to be running at at-least 20MHz. It could also be running faster.
Because you will be using a register to generate the output signal, that signal will be delayed by an FPGA clock period. In general this is not too hard to deal with, you just need to be aware of it.
Cheers,
Dave
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Hi Dave, do you mean like this:
always @(posedge clk_fast)
begin
if (counterScan>14 && counterScan<31)
CK<=clk_200ns;
else
CK<=0
end
where clk_fast should be much faster than clk_200ns, right?
Honored Contributor
