How to reference hierarchy nodes in QII using Verilog

I've never used it, but a while back the "Preserve Fan-out Free Register Node" assignment was added to the Assignment Editor. It is for preserving a register that doesn't drive anything for purposes like simulation.

The on-line help for the assignment:

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Preserve Fan-out Free Register Node logic option

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This option can be set in the Assignment Editor.

A logic option that specifies that the register should be preserved in the design even when it becomes fan-out free.

This option is available for supported device (Arria GX, Cyclone II, Cyclone III, HardCopy II, MAX II, Stratix II, and Stratix III) families.

Scripting Information

Keyword: preserve_fanout_free_node

Settings: on | off

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