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Altera_Forum
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18 years ago

How to reference hierarchy nodes in QII using Verilog

I'm trying to keep redudant logic. Obviously, simply setting "remove redudant logic" off doesn't work. So instead, I want to try to access the outputs from multiple instances of the redudant logic, a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks for your suggestion, Rysc. Ideally I want some dummy logic (no output). But QII removes them even if I use the keep attribute. Now my target is to have a minimal output (just one) and keep all the dummy logic. Maybe WYSIWYG can help if I explicitly use LCELL or FF low level logic.