How to reference hierarchy nodes in QII using Verilog

Is it dummy logic(that doesn't feed anything and therefore gets removed), or is it redundant logic? Turning off remove redundant logic will not do anything for logic that gets trimmed because it's not being used.

There are assignments to keep logic from getting trimmed(I think it's a keep attribute). Another "trick" is to put the logic into a design partition. Part of the rules of a partition is that all IO have to be kept. For example, if you have an output of your partition that is not being used, it still has to be there because maybe on your next compile it does get used, and since that partition could be post-synthesis or post-fit(i.e. not resynthesized), we have to keep all inputs and outputs available for future use. So if you put your logic in a hierarchy and put it into a partition, that should keep it. (Note that within that partition, all nets you want kept must feed an IO of the partition. If they don't feed anything connecting to the IO of the partition, they can be removed since there is nothing that can be done outside of the partition that would cause them to be hooked up.)