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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to reference hierarchy nodes in QII using Verilog

I'm trying to keep redudant logic. Obviously, simply setting "remove redudant logic" off doesn't work. So instead, I want to try to access the outputs from multiple instances of the redudant logic, a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Also turn off remove duplicate registers. If that doesn't do it, it's probably due to something else. And if you have the same logic written twice, why do you want it kept? (They're can be fanout-distance issues, but that's for closing timing, which adding logic structures too isn't going to help.)

You don't reference the .q, you use the signal already hooked up to it, dummy_out[i].