How to reduce the LE countes in my design ?

I would start by targeting a larger device so that the design will compile. Then you can look at fitter reports to see where the gates are being used and figure out if there's anything you can do about it. If the encoder is IP that you purchased then there's probably not much you can do. But if that's the case then the IP vendor should be able to give you guidance on which FPGA family and device you should target. If this is your own IP then it's all on you to find a fit.