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fhw72
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7 years ago

How to properly constrain generated clock and synchronizer?

Hello! In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synch...
fhw72's avatar
fhw72
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7 years ago

Ups... I mixed up the SDC from another similar project; it should have been:

clk_4_77MHz (instead of clk_1Mhz)

What do you mean by Up- and downstream devices?

What frequency do I have to use for the virtual clocks and why two virtual clocks?

I will dig through the tutorials asap... but right now I'm stuck. :-(

Maybe you also have a pointer to a good example too?