How to properly constrain generated clock and synchronizer?

First of all, you need to define two virtual clocks, clock constraints for the clocks that drive the "upstream" and "downstream" devices. These constraints will have no target:

create_clock -period <period> -name <custom name for virtual clock> [-waveform <rise fall>]

Your set_input[output]_delay constraints need to reference the virtual clocks. (What is clk_1MHz?)

Next, the value you use for these constraints is calculated based on the max and min external delays to and from the FPGA for inputs and outputs, respectively.

There's a lot to this, so I'd recommend reviewing this online training for details:

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1118.html