Forum Discussion
fhw72
New Contributor
New ContributorHow to properly constrain generated clock and synchronizer?
Hello! In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synch...
fhw72New Contributor
New Contributor@sstrell:
I'm now trying to constrain the inputs and outputs of my design and appended these lines:
# Constrain the input I/O path
set_input_delay -clock clk_1MHz -max 5 [all_inputs]
set_input_delay -clock clk_1MHz -min 0 [all_inputs]
# Constrain the output I/O path
set_output_delay -clock clk_1MHz -max 5 [all_outputs]
set_output_delay -clock clk_1MHz -min -1 [all_outputs]
5ns is the delay for the level shifters used on the in- and outputs of the design.
However I always get a setup violation?
Do you have an idea what I'm doing wrong?
PS: What should I do with 'altera_reserved_tck' which appears in my ReporT?
