Altera_Forum
Honored Contributor
Honored ContributorHow to process this timing issue?
It seems the data path's delay is too big. Do you have any idea of decrease the data path delay?
Forum Discussion
7 Replies
Altera_ForumThis logic part works well when logic usage is small. Now the logic usage increase to 91%, this timing issue appear.
- Altera_Forum
Try to add more pipeline stages in that path.
- Altera_Forum
Yup, more pipeline stages is the way to go. Unless some of these paths are multicycle (like only enabled every 2+ clocks)?
Or you could specify max_path_delay constraints in your SDC file, but you should only fall on to these as a last resort. - Altera_Forum--- Quote Start --- Try to add more pipeline stages in that path. --- Quote End --- Hi Andrew: It's ok now, thank you for you advise. I just modified the code from
toif hitok/=hitok_q and hitok='1' then--Latch the Coarse Time CT_Latch <= CT_cnt_q; end if;
The relation among "hitok", "hitok_q" and "hitok_2q" is as belowif hitok_q/=hitok_2q and hitok_q='1' then--Latch the Coarse Time CT_Latch <= CT_cnt_q; end if;
.hitok_q <= hitok;hitok_2q <= hitok_q; - Altera_Forum
you use the word latch - is it really a latch, or a register? latches are generally a bad thing...
- Altera_Forum
Agreed, latch is not good for design, especially timing analyzer will have no information to analyze the path correctly. Design assistant will give warning on latches too
- Altera_Forum
Hi Tricky:
You are right, latch is not a good design method. It should not be a latch in fact, i just make some commentary there. The code absolutely is register coding.
