how to prevent this

I don't know why Quartus always determine this register as a clock. and I always fail for some hold timing. if I did a remove clock. then it will pass. but after I save SDC, and do a analysis, then it will complain again. how to prevent quartus to use a register as a clock in time analysis?

following warning happened after I did a

remove_clock -name { i2c_wronly_ecg|cnt[0] }

and

update_timing_netlist

Warning: Node: i2c_wronly_ecg|cnt[0] was determined to be a clock but was found without an associated clock assignment.