How to preserve P&R resultes and resued in another same project ?

When you import the partitions with P&R locked, the timing will be preserved (with a caveat) and any timing constraints should have no effect on the already placed and routed part of the design. The caveat on preserving the timing is that there can be slight timing differences depending on internal crosstalk from other logic in the device. These are usually in the order of less than 50 ps however.