Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to perform logical operation for two signal generated at diiferent clock cycle?
Hi everyone, i have to random binary data signal,one starts at 100ns and ends at 1450ns ,another data signal starts from 14350ns and ends at 15000ns. I want perform xor operation of these two d...
Altera_ForumHonored Contributor
Honored Contributorcan you please provide me the verilog code.. It will be very useful for me. i'm using microsemi Libero Soc 11.4v software to write verilog code.
