Honored Contributor
Honored ContributorHi Kaz,
The tutorial I am following was trying to explain the timing sequence of initial and fork blocks and adding delays . The tutorial says: "To give you a step-by-step description of what happens, Verilog has a trace mode. The example shows the results of running the simulation with the trace mode." I am trying to generate the the timing output as listed in the last section of this email but I have been unsuccessful so for.... Sorry for the lengthy reply but I thought it was necessary. ----------------------------------- Tutorial Example Verilog code: module initial_two_begin; initial begin # 1 $display("Statement 1"); $display("Statement 2"); # 2 $display("Statement 3"); end initial begin $display("Block 2 Statement 1"); # 2 $display("Block 2 Statement 2"); # 2 $display("Block 2 Statement 3"); end endmodule -------------------------------------------- The output is: Block 2 Statement 1 Statement 1 Statement 2 Block 2 Statement 2 Statement 3 Block 2 Statement 3 -------------------------- "Both "initial" blocks start at the same time. However, the first initial block encounters a delay, so the first event that occurs is the $display in the second block. To give you a step-by-step description of what happens, Verilog has a trace mode. Example shows the results of running the simulation with the trace mode." And here is portion of the result that I want to generate and have not been successful: ------------------------------- L3 "i2b.v" (i2b): INITIAL L4 "i2b.v" (i2b): BEGIN L4 "i2b.v" (i2b):# 1 L10 "i2b.v" (i2b): INITIAL L11 "i2b.v" (i2b): BEGIN L12 "i2b.v" (i2b): $display ("Block 2 Statement 1") Block 2 Statement 1 L11 "i2b.v" (i2b):# 2 SIMULATION TIME IS 1 L4 "i2b.v" (i2b):# 1 >>> CONTINUE L5 "i2b.v" (i2b): $display ("Statement 1") Statement 1 L6 "i2b.v" (i2b): $display ("Statement 2") Statement 2 L4 "i2b.v" (i2b):# 2 SIMULATION TIME IS 2 L11 "i2b.v" (12b):# 2 >>> CONTINUE ....... ......
