How to observe Verilogcode execution sequence of Statements in ModelSim 11.1d

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Hi All,

I am using ModelSim 11.1d to simulate my Verilog code and I am trying to understand and watch the sequence of statements executed. How do I see the sequence of events in the simulator? Which commands are needed ?

Thanks,

Charlie

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verilog or vhdl are not software and sequence of execution does not apply.

The parser does go through all statements and may give you syntax errors or other errors but once code is compiled into netlist it is no longer relevant. The netlist is description of generated circuit. Compiler does not build sequentially as it goes through code but looks at all picture then creates netlist.