Forum Discussion
Hi,
As I understand it, you have some inquiries about generating the .qip file for DSP Builder rtl files with relative path. For your information, as I tested HDL generation for an example design ie demo_firs.mdl in DSP Builder 17.0, I can see that the content in the .qip file is using relative path. The following is an example from the qip file for your reference:
# This is the QIP file for DSP Builder for Intel FPGAs system 'demo_firs_FilterSystem'
set_global_assignment -name VHDL_FILE ../rtl/demo_firs/demo_firs_FilterSystem_safe_path.vhd
set_global_assignment -name VHDL_FILE ../rtl/demo_firs/demo_firs_FilterSystem_safe_path.vhd
I notice that if you enable the "Use separate work directory for Quartus Prime project", then .qip file will have absolute path. You can try to disabling this option in your DSP Builder design if it is enabled currently.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin