How to make vhdl testbench for mux 4 to 1 and inputs are 4bits and output is 4bit

Hi! I have problem to make vhdl testbench for mux4/1 witch have 4bit inputs I0 I1 I2 I3 and 4bit output mux_out and select inputs are KO and K1. REMARK: I0 : in std_logic_vector (3 do...