How to make vhdl testbench for mux 4 to 1 and inputs are 4bits and output is 4bit

THIS IS MULTIPLEXER 4/1

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity multiplexer_four_one is

port (

I0 : in std_logic_vector (3 downto 0);

I1 : in std_logic_vector (3 downto 0);

I2 : in std_logic_vector (3 downto 0);

I3 : in std_logic_vector (3 downto 0);

sel :in std_logic_vector (1 downto 0);

mux_out : out std_logic_vector (3 downto 0)

);

end multiplexer_four_one;

architecture Behavioral of multiplexer_four_one is

begin

process(I0,I1,I2,I3,sel)

begin

case sel is

when "00" => mux_out <= I0;

when "01" => mux_out <= I1;

when "10" => mux_out <= I2;

when "11" => mux_out <= I3;

end case;

end process;

end Behavioral;

I need to make 4bit ALU with adder/substract and others components which I will give in text.

SO , I first make 4bit adder/sub with 4bit inputs A and B(that inputs goes also on other inputs components,so its 4bit) like the first component, then the second component is 4bit xor gate with 4bit input/output, the third component is 4bit shift_left

The fourth component is inverter . This four component work some operations. SO after that I have to make ALU unit with multiplexer which will allow some of this components operation

on the outputs of multiplexer Inputs of multiplexer ( I0 I1 I2 I 3 ) are connected with outputs of components.The each input of multiplexer should be connected with 4bit outputs of components. Then inputs of multiplexer must bi 4bit !!!!!!!

So that, select inputs of MUX which is sel in code will allow for example for sel="00" then shift left on the output 4bit signal

Thus, I have problem to make test bench for that ALU respectively multiplexer because hi is indeed ALU. OK?

I do not understand how to give time signal for simulation mux (ALU) in test bench.

DO YOU UNDERSTAND NOW???